// axi_interconnect_1x2.sv
module axi_interconnect_1x2 (
  input  logic        aclk, aresetn,
  // Slave Interface (from NPU)
  input  logic [31:0] s_axi_awaddr, s_axi_araddr,
  input  logic        s_axi_awvalid, s_axi_arvalid, s_axi_wvalid, s_axi_bready, s_axi_rready,
  input  logic [31:0] s_axi_wdata,
  input  logic [3:0]  s_axi_wstrb,
  output logic        s_axi_awready, s_axi_arready, s_axi_wready,
  output logic [31:0] s_axi_rdata,
  output logic [1:0]  s_axi_bresp, s_axi_rresp,
  output logic        s_axi_bvalid, s_axi_rvalid,

  // Master 0: BRAM
  output logic [31:0] m00_axi_awaddr, m00_axi_araddr,
  output logic        m00_axi_awvalid, m00_axi_arvalid, m00_axi_wvalid, m00_axi_bready, m00_axi_rready,
  output logic [31:0] m00_axi_wdata,
  output logic [3:0]  m00_axi_wstrb,
  input  logic        m00_axi_awready, m00_axi_arready, m00_axi_wready,
  input  logic [31:0] m00_axi_rdata,
  input  logic [1:0]  m00_axi_bresp, m00_axi_rresp,
  input  logic        m00_axi_bvalid, m00_axi_rvalid,

  // Master 1: NPU CSR
  output logic [31:0] m01_axi_awaddr, m01_axi_araddr,
  output logic        m01_axi_awvalid, m01_axi_arvalid, m01_axi_wvalid, m01_axi_bready, m01_axi_rready,
  output logic [31:0] m01_axi_wdata,
  output logic [3:0]  m01_axi_wstrb,
  input  logic        m01_axi_awready, m01_axi_arready, m01_axi_wready,
  input  logic [31:0] m01_axi_rdata,
  input  logic [1:0]  m01_axi_bresp, m01_axi_rresp,
  input  logic        m01_axi_bvalid, m01_axi_rvalid
);
  // 地址解码
  logic sel_bram = (s_axi_awaddr[31:16] == 16'h0000) || (s_axi_araddr[31:16] == 16'h0000);
  logic sel_npu  = (s_axi_awaddr[31:28] == 4'h1)     || (s_axi_araddr[31:28] == 4'h1);

  // 简单轮询仲裁 + 地址路由
  assign {m01_axi_awaddr, m00_axi_awaddr} = s_axi_awvalid ? {s_axi_awaddr, s_axi_awaddr} : 64'd0;
  assign m01_axi_awvalid = s_axi_awvalid && sel_npu;
  assign m00_axi_awvalid = s_axi_awvalid && sel_bram;
  // ... 其他信号类似路由
  // 响应合并
  assign s_axi_awready = sel_bram ? m00_axi_awready : m01_axi_awready;
  // ... 类似处理
endmodule